
module top();
	
	reg clk;

	reg[1:0] addr;
	reg in2;
	reg in3;

	reg out1;
	reg out2;

	// rand 

	initial begin
		addr = 0;
		in2 = 0;
		in3 = 0;
		clk = 0;
	end

	always #50 clk = ~clk;

	always @(posedge clk) begin
		in2++;
		in3++;
		addr++;
		$display("out1=%d, out2=%d\n", out1, out2);
	end

	dut d(addr, in2, in3, clk, out1, out2);

endmodule


module dut(addr, in2, in3, clk, out1, out2);

	input[1:0] addr;
	input in2;
	input in3;
	input clk;

	output out1;
	output out2;

	reg[3:0] ram;

	reg ts;
	reg ts2;

	assign out2 = ts2;
	assign out1 = ts;

	always @(posedge clk) begin
		ts2 = ~(in2 & in3);
		ram[addr] = ts2;
		ts = ram[addr];
	end

endmodule


